In this briefing:
1. Intel Touts 3D Logic Scaling, Chiplets & Hybrid Design To Extend Moore’s Law
During an invitation-only Architecture Day held on December 11’th 2018, Intel revealed three key strategies aimed at extending Moore’s Law. The first, 3D Logic packaging, aims to increase effective transistor density by scaling up rather than down, similar to the CoWoS technology introduced by Taiwan Semiconductor in 2012. The second, switching to multiple, smaller “chiplet” processor cores, is required to address the thermal and yield challenges precipitated by the progression of ever larger multi-core monolithic processor die and is the key foundation underpinning Advanced Micro Devices‘s Zen-based architecture. The third is a hybrid architecture aimed at reducing power consumption and clearly reminiscent of ARM’s big.LITTLE approach which was first introduced some six years ago and now widely used today in smartphone and tablet SOCs.
At the event, Intel showcased their first product based on these three key concepts and it features a large Core processor combined with four smaller Atom processors, all manufactured on the same piece of silicon, an approach the company refers to as Hybrid x86. Intel confirmed that it will be the basis for a new line of products set to launch in the second half of 2019.
They say that imitation is the sincerest form of flattery and, based on what Intel had to say at its Architecture Day, TSMC, AMD and ARM will likely be flattered in equal measure.
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